Core Technologies-Innoscience

8-inch GaN-on-Si Epitaxy
8-inch GaN-on-Si Process Technology
8-inch GaN-on-Si Process Technology

MOCVD Reactors

Innoscience uses the latest Aixtron G5+C™ MOCVD reactors to grow our 8-inch GaN-on-Si wafers. Aixtron MOCVD reactor G5+C™ reactors to grow our 8-inch GaN-on-Si wafers.

8-inch GaN-on-Si Epi-Buffer

Innoscience has developed proprietary 8-inch GaN-on-Si epi-buffer technology optimized for both high-voltage (HV) and low-voltage (LV) devices.

By controlling our epitaxy technology in-house, we rapidly adapt epi-processes to meet specific customer requirements and application needs.

We continuously optimize and enhance epi-performance and throughput to deliver high-performance, cost-effective GaN-on-Si technology.

Epitaxy Production & Capability

Innoscience grows more than 10,000 wafers per month, which are processed into HV and LV devices shipped to customers worldwide.

Our GaN-on-Si epitaxial process consistently produces uniform, reproducible, crack-free epi-wafers with low dislocation density and minimal defects.

8-inch GaN-on-Si wafers

Silicon technology has been scaling in terms of wafer size over the past 40 years going from small inches up to 8-inch and today 12-inches. The aim was always the same: simultaneously process more devices per wafer and thus lower their cost.

Similarly, while other GaN players are still today on 4-inch or 6-inch wafer size, Innoscience from the very beginning is strategically adopting 8-inch wafer size. By processing an 8-inch GaN-on-Si wafer, Innoscience obtains 80% more devices per wafer with respect to what would be possible with a 6-inch wafer. Obviously, this has a direct impact on the device cost allowing Innoscience to make GaN device technology affordable.

High-throughput Silicon-compatible manufacturing process

Silicon technology has been in mass production for past 40 years. Silicon device manufactures supported by the tool makers, have optimized their process in terms of throughput (wafer-per-hour) and quality in order to utilize every inch of their Silicon wafer and produce as many wafers as possible with their line.

For this reason, Innoscience has decided to equip its lines with brand new 8-inch high-throughput Silicon manufacturing tools (e.g. ASML scanners) and to develop a Silicon compatible process flow (e.g. gold free metals, planarize process, topography defines by etching process rather than lift-off etc…).

Therefore, Innoscience has leveraged years of learning and optimization for the mass production of Silicon technology for the production of cost-effective 8-inch GaN-on-Si transistors.

High yield

Obtaining a large number of device per wafer is not enough if the process yield is not optimized.

Being Innoscience an IDM and thus controlling the full manufacturing flow (from epitaxy until the transistor completion), Innoscience could improve every technology aspect in order to obtain both high wafer and device yield.

Innoscience has optimized the epitaxy processing in order to obtain uniform, reproducible and robust 8-inch GaN-on-Si epi-wafers, which are the basis for the device processing. Next to this, Innoscience has optimized the process technology, enlarge process windows etc.. in order to obtain a reproducible process and a large number of good device per wafer.

Today, Innoscience has been producing more than 10,000 wafers/month with excellent reproducibility and high wafer and device yield.

High-throughput Silicon-compatible manufacturing process

The power semiconductor market demands devices that show normally-off operation, which means that there is no current conduction when the transistor’s gate is set at 0V.

The natural form of GaN HEMTs (High Electron Mobility Transistors) is normally-on or so-called depletion mode (d-mode), which requires special drivers or to be placed in a cascode package solutions to realize normally-off operation.

Innoscience’s GaN HEMTs are intrinsically normally-off or so-called enhancement mode (e-mode) devices. The normally-off operation is realized by growing a p-GaN layer on top of the AlGaN barrier, deposition and patterning of a gate metal and then selective recessing the p-GaN layer over the AlGaN barrier.

The gate metal layer forms a (Schottky) contact with the p-GaN layer, and, as a consequence, the potential in the channel at the equilibrium is lifted-up therefore realizing normally-off/e-mode operation.

Low Specific R_{DS_ON}

Innoscience technology is optimized for high performance and reliability as well as for mass production and cost reduction. One of the key parameter defining the technology performance is the specific R_{DS_ON} that is the on-resistance per unit area (i.e. the smaller the specific R_{DS_ON} the smaller a device can be design for a given on-resistance; the smaller the device, the larger the number of devices that can be placed into a wafer and thus the lower the cost).

Innoscience has developed a strain enhancement layer technology, which consists of the deposition of a specific layer after the gate stack definition. The stress modulation created by the strain enhancement layer induces additional piezoelectric polarizations; this causes the 2DEG density to increase and thus the sheet resistance to decrease by 66% compared with a device without strain layer.

Since the strain enhancement layer is deposited after the gate formation, it only affects the resistance in the access region and it does not impact other device parameters such as threshold, leakage etc..

Thanks to this technology, Innosience’s GaN-on-Si e-mode HEMTs show very low specific on-resistance.

Excellent performance

Innoscience’s GaN technology is optimized for performance and reliability.

One of the key technology aspect of Innoscience’s GaN technology is the very low dynamic R_{DS_ON} over the full temperature and voltage range. This means that the on-resistance of the device does not increase when used in real power switching applications.

Not optimized GaN technology often shows a drift of the on-resistance when a high voltage is applied to the drain side of the device while the device is switched off, as the device would experience in real application. This is not only detrimental for the overall system performance, as higher resistance means higher loss, but it is also detrimental for the device reliability as the device become hotter and more prone to failure.

This is one of the reason why Innoscience’s GaN technology shows excellent temperature stability in real application without overheating.

Innoscience has achieved this by carefully optimizing both epitaxy as well as device process technology.